1. Field of the Invention
The present invention relates to an interrupt controller, and more specifically to an interrupt controller for use in a microcomputer, capable of designating the order of preference or the priority level to interrupt requests.
2. Description of Related Art
A microcomputer includes therein an interrupt controller for processing various interrupt requests. A typical conventional interrupt controller includes a scan counter which sequentially scans a given number of priority levels for realizing such an interrupt priority level control that when an interrupt processing having a low priority level is under execution, another interrupt processing having a high priority level can be executed by interrupt, but, when an interrupt processing having a high priority level is under execution, another interrupt processing having a low priority level cannot be executed.
However, in the conventional interrupt controller, since the priority levels are sequentially scanned by the scan counter, the larger the number of priority levels is, the longer the time for one cycle of the scanning operation becomes. In recent advanced microcomputers, the number of interrupt request signals is large, and the number of priority levels also becomes large in order to realize an elaborate control. As a result, a maximum time from the moment an interrupt signal is generated to the moment the interrupt signal is acknowledged becomes long. This is not suitable to microcomputers adapted for a real time control.